switches 175 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.FLT_BASE); switches 177 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.cpu_num); switches 179 src/dps8/dps8_cpu.c (unsigned long long)cpus[cpu_unit_idx].switches.data_switches); switches 181 src/dps8/dps8_cpu.c PBI_64((unsigned long long)cpus[cpu_unit_idx].switches.data_switches)); switches 185 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.addr_switches); switches 187 src/dps8/dps8_cpu.c PBI_32(cpus[cpu_unit_idx].switches.addr_switches)); switches 193 src/dps8/dps8_cpu.c 'A' + i, cpus[cpu_unit_idx].switches.enable [i]); switches 195 src/dps8/dps8_cpu.c 'A' + i, cpus[cpu_unit_idx].switches.init_enable [i]); switches 197 src/dps8/dps8_cpu.c 'A' + i, cpus[cpu_unit_idx].switches.assignment [i]); switches 199 src/dps8/dps8_cpu.c 'A' + i, cpus[cpu_unit_idx].switches.interlace [i]); switches 201 src/dps8/dps8_cpu.c 'A' + i, cpus[cpu_unit_idx].switches.store_size [i]); switches 204 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.procMode == procModeMultics ? "Multics" : cpus[cpu_unit_idx].switches.procMode == procModeGCOS ? "GCOS" : "???", switches 205 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.procMode); switches 207 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable_cache ? "Enabled" : "Disabled"); switches 209 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.sdwam_enable ? "Enabled" : "Disabled"); switches 211 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.ptwam_enable ? "Enabled" : "Disabled"); switches 503 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.FLT_BASE = (uint) v; switches 505 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.cpu_num = (uint) v; switches 507 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.data_switches = (word36) v; switches 521 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.data_switches = d; switches 524 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.addr_switches = (word18) v; switches 526 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.procMode = v ? procModeMultics : procModeGCOS; switches 537 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.assignment [port_num] = (uint) v; switches 539 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [port_num] = (uint) v; switches 541 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [port_num] = (uint) v; switches 543 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.init_enable [port_num] = (uint) v; switches 570 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.store_size [port_num] = (uint) v; switches 573 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable_cache = (uint) v ? true : false; switches 575 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.sdwam_enable = (uint) v ? true : false; switches 577 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.ptwam_enable = (uint) v ? true : false; switches 628 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].isolts_switches_save = cpus[cpu_unit_idx].switches; switches 631 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.data_switches = 00000030714000; switches 632 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.addr_switches = 0100150; switches 635 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.assignment [0] = 0; switches 636 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [0] = false; switches 637 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [0] = false; switches 638 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.init_enable [0] = false; switches 639 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.store_size [0] = store_sz; switches 641 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.assignment [1] = 0; switches 642 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [1] = false; switches 643 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [1] = true; switches 644 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.init_enable [1] = false; switches 645 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.store_size [1] = store_sz; switches 647 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.assignment [2] = 0; switches 648 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [2] = false; switches 649 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [2] = false; switches 650 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.init_enable [2] = false; switches 651 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.store_size [2] = store_sz; switches 653 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.assignment [3] = 0; switches 654 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [3] = false; switches 655 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [3] = false; switches 656 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.init_enable [3] = false; switches 657 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.store_size [3] = store_sz; switches 660 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.assignment [4] = 0; switches 661 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [4] = false; switches 662 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [4] = false; switches 663 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.init_enable [4] = false; switches 664 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.store_size [4] = 3; switches 666 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.assignment [5] = 0; switches 667 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [5] = false; switches 668 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [5] = false; switches 669 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.init_enable [5] = false; switches 670 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.store_size [5] = 3; switches 672 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.assignment [6] = 0; switches 673 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [6] = false; switches 674 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [6] = false; switches 675 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.init_enable [6] = false; switches 676 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.store_size [6] = 3; switches 678 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.assignment [7] = 0; switches 679 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [7] = false; switches 680 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [7] = false; switches 681 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.init_enable [7] = false; switches 682 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.store_size [7] = 3; switches 686 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [1] = true; switches 690 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches = cpus[cpu_unit_idx].isolts_switches_save; switches 836 src/dps8/dps8_cpu.c cpun->switches.assignment[port_num] = port_num; switches 837 src/dps8/dps8_cpu.c cpun->switches.interlace[port_num] = 0; switches 838 src/dps8/dps8_cpu.c cpun->switches.store_size[port_num] = 2; switches 839 src/dps8/dps8_cpu.c cpun->switches.enable[port_num] = 1; switches 840 src/dps8/dps8_cpu.c cpun->switches.init_enable[port_num] = 1; switches 843 src/dps8/dps8_cpu.c cpun->switches.assignment[port_num] = 0; switches 844 src/dps8/dps8_cpu.c cpun->switches.interlace[port_num] = 0; switches 845 src/dps8/dps8_cpu.c cpun->switches.store_size[port_num] = 0; switches 846 src/dps8/dps8_cpu.c cpun->switches.enable[port_num] = 0; switches 847 src/dps8/dps8_cpu.c cpun->switches.init_enable[port_num] = 0; switches 861 src/dps8/dps8_cpu.c cpun->switches.assignment[port_num] = port_num; switches 862 src/dps8/dps8_cpu.c cpun->switches.interlace[port_num] = 0; switches 863 src/dps8/dps8_cpu.c cpun->switches.store_size[port_num] = 7; switches 864 src/dps8/dps8_cpu.c cpun->switches.enable[port_num] = 1; switches 865 src/dps8/dps8_cpu.c cpun->switches.init_enable[port_num] = 1; switches 868 src/dps8/dps8_cpu.c cpun->switches.assignment[port_num] = 0; switches 869 src/dps8/dps8_cpu.c cpun->switches.interlace[port_num] = 0; switches 870 src/dps8/dps8_cpu.c cpun->switches.store_size[port_num] = 0; switches 871 src/dps8/dps8_cpu.c cpun->switches.enable[port_num] = 0; switches 872 src/dps8/dps8_cpu.c cpun->switches.init_enable[port_num] = 0; switches 964 src/dps8/dps8_cpu.c cpu.cu.SD_ON = cpu.switches.sdwam_enable ? 1 : 0; switches 965 src/dps8/dps8_cpu.c cpu.cu.PT_ON = cpu.switches.ptwam_enable ? 1 : 0; switches 1299 src/dps8/dps8_cpu.c if (! cpu.switches.enable [port_num]) switches 1311 src/dps8/dps8_cpu.c uint store_size = cpu.switches.store_size [port_num]; switches 1341 src/dps8/dps8_cpu.c uint base_addr_wds = sz_wds * cpu.switches.assignment[port_num]; switches 1413 src/dps8/dps8_cpu.c if (sscanf (buffer, "sn: %u", & cpu.switches.serno) == 1) switches 1417 src/dps8/dps8_cpu.c sim_msg ("%s CPU serial number: %u\n", sim_name, cpu.switches.serno); switches 1425 src/dps8/dps8_cpu.c cpus[cpun].switches.serno = sn; switches 1429 src/dps8/dps8_cpu.c sim_name, cpun, cpus[cpun].switches.serno); switches 1568 src/dps8/dps8_cpu.c cpus [0].switches.FLT_BASE = 2; // Some of the UnitTests assume this switches 1836 src/dps8/dps8_cpu.c cpu.cu.IWB = cpu.switches.data_switches; switches 3190 src/dps8/dps8_cpu.c uint fltAddress = (cpu.switches.FLT_BASE << 5) & 07740; switches 4663 src/dps8/dps8_cpu.c putbits36_3 (& rsw2, 33, cpus[cpuNo].switches.cpu_num & 07LL); switches 4673 src/dps8/dps8_cpu.c sprintf (serial, "%-11u", cpus[cpuNo].switches.serno); switches 1598 src/dps8/dps8_cpu.h switches_t switches; switches 388 src/dps8/dps8_ins.c putbits36_3 (& words[2], 27, (word3) cpu.switches.cpu_num); switches 3414 src/dps8/dps8_ins.c if (cpu.switches.procMode == procModeGCOS) switches 7834 src/dps8/dps8_ins.c cpu.rA = cpu.switches.data_switches; switches 7865 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.assignment [0] & 07LL) switches 7867 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [0] & 01LL) switches 7869 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.init_enable [0] & 01LL) switches 7871 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [0] ? 1LL:0LL) switches 7873 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.store_size [0] & 07LL) switches 7876 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.assignment [1] & 07LL) switches 7878 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [1] & 01LL) switches 7880 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.init_enable [1] & 01LL) switches 7882 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [1] ? 1LL:0LL) switches 7884 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.store_size [1] & 07LL) switches 7887 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.assignment [2] & 07LL) switches 7889 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [2] & 01LL) switches 7891 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.init_enable [2] & 01LL) switches 7893 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [2] ? 1LL:0LL) switches 7895 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.store_size [2] & 07LL) switches 7898 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.assignment [3] & 07LL) switches 7900 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [3] & 01LL) switches 7902 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.init_enable [3] & 01LL) switches 7904 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [3] ? 1LL:0LL) switches 7906 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.store_size [3] & 07LL) switches 7979 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.interlace[0] == 2 ? switches 7981 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.interlace[1] == 2 ? switches 7983 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.interlace[2] == 2 ? switches 7985 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.interlace[3] == 2 ? switches 7997 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.FLT_BASE & 0177LL) switches 8022 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.enable_cache ? 1 : 0) switches 8027 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.procMode) /* 0b1 DPS8M */ switches 8029 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.procMode & 1U) switches 8051 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.cpu_num & 07LL) switches 8088 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.assignment [4] & 07LL) switches 8090 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [4] & 01LL) switches 8092 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.init_enable [4] & 01LL) switches 8094 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [4] ? 1LL:0LL) switches 8096 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.store_size [4] & 07LL) switches 8099 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.assignment [5] & 07LL) switches 8101 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [5] & 01LL) switches 8103 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.init_enable [5] & 01LL) switches 8105 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [5] ? 1LL:0LL) switches 8107 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.store_size [5] & 07LL) switches 8110 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.assignment [6] & 07LL) switches 8112 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [6] & 01LL) switches 8114 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.init_enable [6] & 01LL) switches 8116 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [6] ? 1LL:0LL) switches 8118 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.store_size [6] & 07LL) switches 8121 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.assignment [7] & 07LL) switches 8123 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [7] & 01LL) switches 8125 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.init_enable [7] & 01LL) switches 8127 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [7] ? 1LL:0LL) switches 8129 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.store_size [7] & 07LL) switches 8150 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [0] == 2 ? switches 8152 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [1] == 2 ? switches 8154 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [2] == 2 ? switches 8156 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [3] == 2 ? switches 8159 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [4] == 2 ? switches 8161 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [5] == 2 ? switches 8163 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [6] == 2 ? switches 8165 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [7] == 2 ? switches 9289 src/simh/scp.c t_stat sim_exp_set (EXPECT *exp, const char *match, int32 cnt, uint32 after, int32 switches, const char *act) switches 9300 src/simh/scp.c if (switches & EXP_TYP_REGEX) { switches 9305 src/simh/scp.c if (switches & EXP_TYP_REGEX_I) { switches 9318 src/simh/scp.c (exp->rules[i].switches & EXP_TYP_PERSIST)) switches 9344 src/simh/scp.c ep->switches = switches; /* set switches */ switches 9351 src/simh/scp.c if (switches & EXP_TYP_REGEX) { switches 9389 src/simh/scp.c uint32 compare_size = (exp->rules[i].switches & EXP_TYP_REGEX) ? MAX(10 * strlen(ep->match_pattern), 1024) : exp->rules[i].size; switches 9405 src/simh/scp.c if (ep->switches & EXP_TYP_PERSIST) switches 9407 src/simh/scp.c if (ep->switches & EXP_TYP_CLEARALL) switches 9409 src/simh/scp.c if (ep->switches & EXP_TYP_REGEX) switches 9411 src/simh/scp.c if (ep->switches & EXP_TYP_REGEX_I) switches 9481 src/simh/scp.c if (ep->switches & EXP_TYP_REGEX) { switches 9544 src/simh/scp.c int32 switches = ep->switches; switches 9552 src/simh/scp.c if (ep->switches & EXP_TYP_CLEARALL) /* Clear-all expect rule? */ switches 9555 src/simh/scp.c if (!(ep->switches & EXP_TYP_PERSIST)) /* One shot expect rule? */ switches 9559 src/simh/scp.c (switches & EXP_TYP_TIME) ? switches 187 src/simh/scp.h t_stat sim_exp_set (EXPECT *exp, const char *match, int32 cnt, uint32 after, int32 switches, const char *act); switches 617 src/simh/scp.h const char *switches, switches 620 src/simh/sim_defs.h int32 switches; /* flags */