MFk              1179 src/dps8/dps8_eis.c     word18 MFk = e -> MF [k - 1];
MFk              1181 src/dps8/dps8_eis.c     if (MFk & MFkID)
MFk              1336 src/dps8/dps8_eis.c     word18 MFk = e -> MF [k - 1];
MFk              1409 src/dps8/dps8_eis.c     if (MFk & MFkAR)
MFk              1437 src/dps8/dps8_eis.c     if (MFk & MFkRL)
MFk              1472 src/dps8/dps8_eis.c     word36 r = getMFReg36 (MFk & 017, allowDU, true, mod_fault); // allow du based on instruction, allow n,ic
MFk              1474 src/dps8/dps8_eis.c     if ((MFk & 017) == 4)   // reg == IC ?
MFk              1656 src/dps8/dps8_eis.c     word18 MFk = e->MF[k-1];
MFk              1666 src/dps8/dps8_eis.c     if (MFk & MFkAR)
MFk              1711 src/dps8/dps8_eis.c     if (MFk & MFkRL)
MFk              1721 src/dps8/dps8_eis.c     word36 r = getMFReg36(MFk & 017, false, true, mod_fault); // disallow du, allow n, ic
MFk              1722 src/dps8/dps8_eis.c     if ((MFk & 017) == 4)   // reg == IC ?
MFk              1834 src/dps8/dps8_eis.c     word18 MFk = e->MF[k-1];
MFk              1847 src/dps8/dps8_eis.c     if (MFk & MFkAR)
MFk              1873 src/dps8/dps8_eis.c     if (MFk & MFkRL)
MFk              1896 src/dps8/dps8_eis.c     word36 r = getMFReg36(MFk & 017, false, true, mod_fault);  // disallow du, allow n,ic
MFk              1897 src/dps8/dps8_eis.c     if ((MFk & 017) == 4)   // reg == IC ?