reg 327 src/dps8/dps8_eis.c static word36 getCrAR (word4 reg) reg 329 src/dps8/dps8_eis.c if (reg == 0) reg 332 src/dps8/dps8_eis.c if (reg & 010) /* Xn */ reg 333 src/dps8/dps8_eis.c return cpu.rX [X (reg)]; reg 335 src/dps8/dps8_eis.c switch (reg) reg 1293 src/dps8/dps8_eis.c uint reg = opDesc & 017; reg 1295 src/dps8/dps8_eis.c address += getMFReg18 (reg, false, true, mod_fault); // ID=1: disallow du, allow n,ic reg 1439 src/dps8/dps8_eis.c uint reg = opDesc & 017; reg 1441 src/dps8/dps8_eis.c e -> N [k - 1] = (uint) getMFReg36 (reg, false, false, mod_fault); // RL=1: disallow du,n,ic reg 1713 src/dps8/dps8_eis.c uint reg = opDesc & 017; reg 1714 src/dps8/dps8_eis.c e->N[k-1] = getMFReg18(reg, false, false, mod_fault) & 077; // RL=1: disallow du,n,ic reg 1875 src/dps8/dps8_eis.c uint reg = opDesc & 017; reg 1876 src/dps8/dps8_eis.c e->N[k-1] = getMFReg36(reg, false, false, mod_fault) & 077777777; // RL=1: disallow du,n,ic reg 1877 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "bitstring k %d RL reg %u val %"PRIo64"\n", k, reg, (word36)e->N[k-1]); reg 1965 src/dps8/dps8_eis.c word4 reg = GET_TD (cpu.cu.IWB); // 4-bit register modification (None except reg 1968 src/dps8/dps8_eis.c word36 ur = getCrAR (reg); reg 2044 src/dps8/dps8_eis.c word4 reg = GET_TD (cpu.cu.IWB); // 4-bit register modification (None except reg 2047 src/dps8/dps8_eis.c word36 ur = getCrAR (reg); reg 2091 src/dps8/dps8_eis.c word6 reg = GET_TD (cpu.cu.IWB); // 4-bit register modification (None except reg 2094 src/dps8/dps8_eis.c word36 rcnt = getCrAR (reg); reg 2108 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "axbd sz %d ARn 0%o address 0%o reg 0%o r 0%o\n", sz, ARn, address, reg, r); reg 2163 src/dps8/dps8_eis.c word4 reg = (word4) GET_TD (cpu.cu.IWB); reg 2165 src/dps8/dps8_eis.c word24 r = getCrAR ((word4) reg) & MASK24; reg 2225 src/dps8/dps8_eis.c reg 2228 src/dps8/dps8_eis.c reg 2364 src/dps8/dps8_eis.c word4 reg = (word4) GET_TD (cpu.cu.IWB); reg 2367 src/dps8/dps8_eis.c int32_t r = (int32_t) (getCrAR (reg) & MASK18); reg 2371 src/dps8/dps8_eis.c "awd ARn 0%o address 0%o reg 0%o r 0%o\n", ARn, address, reg, r); reg 2401 src/dps8/dps8_eis.c word4 reg = (word4) GET_TD (cpu.cu.IWB); reg 2403 src/dps8/dps8_eis.c word24 r = getCrAR ((word4) reg) & MASK24; reg 2439 src/dps8/dps8_eis.c word4 reg = (word4) GET_TD (cpu.cu.IWB); reg 2442 src/dps8/dps8_eis.c int32_t r = (int32_t) (getCrAR (reg) & MASK18); reg 2445 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "swd ARn 0%o address 0%o reg 0%o r 0%o\n", ARn, address, reg, r); reg 2477 src/dps8/dps8_eis.c word4 reg = (word4) GET_TD (cpu.cu.IWB); reg 2480 src/dps8/dps8_eis.c word21 r = getCrAR (reg) & MASK21;; reg 2484 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "s9bd ARn 0%o address 0%o reg 0%o r 0%o\n", ARn, address, reg, r); reg 2758 src/dps8/dps8_eis.c word4 reg = (word4) GET_TD (cpu.cu.IWB); // 4-bit register modification (None except reg 2766 src/dps8/dps8_eis.c word36 rcnt = getCrAR (reg); reg 2784 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "asxbd sz %d ARn 0%o address 0%o reg 0%o r 0%o\n", sz, ARn, address, reg, r); reg 7348 src/dps8/dps8_ins.c uint reg = cpu.tweaks.l68_mode ? L68_APU_HIST_REG : DPS8M_APU_HIST_REG; reg 7349 src/dps8/dps8_ins.c cpu.Ypair[0] = cpu.history[reg] [cpu.history_cyclic[reg]][0]; reg 7350 src/dps8/dps8_ins.c cpu.Ypair[1] = cpu.history[reg] [cpu.history_cyclic[reg]][1]; reg 7351 src/dps8/dps8_ins.c cpu.history_cyclic[reg] = (cpu.history_cyclic[reg] + 1) % N_MODEL_HIST_SIZE; reg 7396 src/dps8/dps8_ins.c uint reg = cpu.tweaks.l68_mode ? L68_DU_HIST_REG : DPS8M_EAPU_HIST_REG; reg 7397 src/dps8/dps8_ins.c cpu.Ypair[0] = cpu.history[reg] [cpu.history_cyclic[reg]][0]; reg 7398 src/dps8/dps8_ins.c cpu.Ypair[1] = cpu.history[reg] [cpu.history_cyclic[reg]][1]; reg 7399 src/dps8/dps8_ins.c cpu.history_cyclic[reg] = (cpu.history_cyclic[reg] + 1) % N_MODEL_HIST_SIZE; reg 7418 src/dps8/dps8_ins.c uint reg = cpu.tweaks.l68_mode ? L68_OU_HIST_REG : DPS8M_DU_OU_HIST_REG; reg 7419 src/dps8/dps8_ins.c cpu.Ypair[0] = cpu.history[reg] [cpu.history_cyclic[reg]][0]; reg 7420 src/dps8/dps8_ins.c cpu.Ypair[1] = cpu.history[reg] [cpu.history_cyclic[reg]][1]; reg 7421 src/dps8/dps8_ins.c cpu.history_cyclic[reg] = (cpu.history_cyclic[reg] + 1) % N_MODEL_HIST_SIZE; reg 94 src/dps8/hdbg.c } reg; reg 257 src/dps8/hdbg.c hevents[p].reg.type = type; reg 258 src/dps8/hdbg.c hevents[p].reg.data = data; reg 264 src/dps8/hdbg.c hevents[p].reg.type = type; reg 265 src/dps8/hdbg.c hevents[p].reg.data = data; reg 408 src/dps8/hdbg.c if (p->reg.type == hreg_IR) reg 414 src/dps8/hdbg.c regNames[p->reg.type], reg 415 src/dps8/hdbg.c (unsigned long long int)p->reg.data, reg 416 src/dps8/hdbg.c TSTF (p->reg.data, I_ZERO), reg 417 src/dps8/hdbg.c TSTF (p->reg.data, I_NEG), reg 418 src/dps8/hdbg.c TSTF (p->reg.data, I_CARRY), reg 419 src/dps8/hdbg.c TSTF (p->reg.data, I_OFLOW), reg 420 src/dps8/hdbg.c TSTF (p->reg.data, I_TALLY)); reg 421 src/dps8/hdbg.c else if (p->reg.type >= hreg_X0 && p->reg.type <= hreg_X7) reg 427 src/dps8/hdbg.c regNames[p->reg.type], reg 428 src/dps8/hdbg.c (unsigned long long int)p->reg.data); reg 435 src/dps8/hdbg.c regNames[p->reg.type], reg 436 src/dps8/hdbg.c (unsigned long long int)p->reg.data); reg 441 src/dps8/hdbg.c if (p->reg.type >= hreg_PR0 && p->reg.type <= hreg_PR7) reg 447 src/dps8/hdbg.c regNames[p->reg.type], reg 457 src/dps8/hdbg.c regNames[p->reg.type], reg 471 src/dps8/hdbg.c regNames[p->reg.type],