op 3983 src/decNumber/decNumber.c decContext *set, Flag op, uInt *status) { op 4054 src/decNumber/decNumber.c op & (REMAINDER | REMNEAR)) { // as is remainder of infinity op 4065 src/decNumber/decNumber.c if (op&(REMAINDER|REMNEAR)) { op 4074 src/decNumber/decNumber.c if (op&DIVIDE) { op 4092 src/decNumber/decNumber.c if (op&(REMAINDER|REMNEAR)) *status|=DEC_Invalid_operation; op 4106 src/decNumber/decNumber.c if (op&DIVIDE) { op 4112 src/decNumber/decNumber.c else if (op&DIVIDEINT) { op 4137 src/decNumber/decNumber.c if (exponent<0 && !(op==DIVIDE)) { op 4138 src/decNumber/decNumber.c if (op&DIVIDEINT) { op 4148 src/decNumber/decNumber.c if (op&REMAINDER || exponent<-1) { op 4189 src/decNumber/decNumber.c if (!(op&DIVIDE)) var1units++; op 4240 src/decNumber/decNumber.c if (!(op&DIVIDE)) { op 4343 src/decNumber/decNumber.c if (op&(REMAINDER|REMNEAR)) break; op 4344 src/decNumber/decNumber.c if ((op&DIVIDE) && (exponent<=maxexponent)) break; op 4349 src/decNumber/decNumber.c if (exponent==0 && !(op&DIVIDE)) break; op 4371 src/decNumber/decNumber.c if (op&DIVIDE) { op 4411 src/decNumber/decNumber.c if (op & (REMAINDER|REMNEAR)) { op 4460 src/decNumber/decNumber.c if (op&REMNEAR) { op 4544 src/decNumber/decNumber.c if (!set->extended && (op==DIVIDE)) decTrim(res, set, 0, 1, &dropped); op 5729 src/decNumber/decNumber.c Flag op, uInt *status) { op 5756 src/decNumber/decNumber.c if (op==COMPTOTAL) { // total ordering op 5775 src/decNumber/decNumber.c if (op==COMPARE); // result will be NaN op 5776 src/decNumber/decNumber.c else if (op==COMPSIG) // treat qNaN as sNaN op 5778 src/decNumber/decNumber.c else if (op==COMPTOTAL) { // total ordering, always finite op 5801 src/decNumber/decNumber.c op=COMPMAX; op 5807 src/decNumber/decNumber.c op=COMPNAN; // use special path op 5812 src/decNumber/decNumber.c if (op==COMPMAXMAG || op==COMPMINMAG) result=decCompare(lhs, rhs, 1); op 5818 src/decNumber/decNumber.c if (op==COMPARE || op==COMPSIG ||op==COMPTOTAL) { // returning signum op 5819 src/decNumber/decNumber.c if (op==COMPTOTAL && result==0) { op 5834 src/decNumber/decNumber.c else if (op==COMPNAN); // special, drop through op 5845 src/decNumber/decNumber.c op=COMPMAX; op 5867 src/decNumber/decNumber.c if (op==COMPMIN || op==COMPMINMAG) result=-result; op 4447 src/dps8/dps8_cpu.c void add_l68_APU_history (enum APUH_e op) op 4452 src/dps8/dps8_cpu.c w0 = op; // set 17-24 FDSPTW/.../FAP bits op 538 src/dps8/dps8_cpu.h word36 op [3]; // raw operand descriptors op 539 src/dps8/dps8_cpu.h #define OP1 op [0] // 1st descriptor (2nd ins word) op 540 src/dps8/dps8_cpu.h #define OP2 op [1] // 2nd descriptor (3rd ins word) op 541 src/dps8/dps8_cpu.h #define OP3 op [2] // 3rd descriptor (4th ins word) op 2383 src/dps8/dps8_cpu.h void add_l68_APU_history (enum APUH_e op); op 1188 src/dps8/dps8_eis.c word36 opDesc = e -> op [k - 1]; op 1307 src/dps8/dps8_eis.c e -> op [k - 1] = EISRead (& e -> addr [k - 1]); op 1347 src/dps8/dps8_eis.c word36 opDesc = e -> op [k - 1]; op 1601 src/dps8/dps8_eis.c word36 opDesc = e -> op [k - 1]; op 1660 src/dps8/dps8_eis.c word36 opDesc = e->op[k-1]; op 1835 src/dps8/dps8_eis.c word36 opDesc = e->op[k-1]; op 3003 src/dps8/dps8_eis.c if (!(e->MF[0] & MFkID) && e -> op [0] & 0000000010000) op 3014 src/dps8/dps8_eis.c op 3144 src/dps8/dps8_eis.c if (!(e->MF[0] & MFkID) && e -> op [0] & 0000000010000) op 3148 src/dps8/dps8_eis.c if (!(e->MF[2] & MFkID) && e -> op [2] & 0000000777660) op 3327 src/dps8/dps8_eis.c if (!(e->MF[0] & MFkID) && e -> op [0] & 0000000010000) op 3331 src/dps8/dps8_eis.c if (!(e->MF[2] & MFkID) && e -> op [2] & 0000000777660) op 3526 src/dps8/dps8_eis.c if (!(e->MF[0] & MFkID) && e -> op [0] & 0000000010000) op 3530 src/dps8/dps8_eis.c if (!(e->MF[2] & MFkID) && e -> op [2] & 0000000777660) op 3694 src/dps8/dps8_eis.c if (!(e->MF[0] & MFkID) && e -> op [0] & 0000000010000) op 3702 src/dps8/dps8_eis.c if (!(e->MF[2] & MFkID) && e -> op [2] & 0000000777660) op 3895 src/dps8/dps8_eis.c if (!(e->MF[0] & MFkID) && e -> op [0] & 0000000010000) op 3899 src/dps8/dps8_eis.c if (!(e->MF[1] & MFkID) && e -> op [1] & 0000000777660) op 3903 src/dps8/dps8_eis.c if (!(e->MF[2] & MFkID) && e -> op [2] & 0000000777660) op 4090 src/dps8/dps8_eis.c if (!(e->MF[0] & MFkID) && e -> op [0] & 0000000010000) op 4094 src/dps8/dps8_eis.c if (!(e->MF[1] & MFkID) && e -> op [1] & 0000000777660) op 4098 src/dps8/dps8_eis.c if (!(e->MF[2] & MFkID) && e -> op [2] & 0000000777660) op 4329 src/dps8/dps8_eis.c if (!(e->MF[0] & MFkID) && e -> op [0] & 0000000010000) op 4333 src/dps8/dps8_eis.c if (!(e->MF[1] & MFkID) && e -> op [1] & 0000000010000) op 4727 src/dps8/dps8_eis.c if (!(e->MF[0] & MFkID) && e -> op [0] & 0000000010000) op 4731 src/dps8/dps8_eis.c if (!(e->MF[1] & MFkID) && e -> op [1] & 0000000010000) op 6683 src/dps8/dps8_eis.c if (!(e->MF[0] & MFkID) && e -> op [0] & 0000000010000) op 6688 src/dps8/dps8_eis.c op 6692 src/dps8/dps8_eis.c if (!(e->MF[1] & MFkID) && e -> op [1] & 0000000010000) op 6696 src/dps8/dps8_eis.c if (!(e->MF[2] & MFkID) && e -> op [2] & 0000000010000) op 6813 src/dps8/dps8_eis.c op 6817 src/dps8/dps8_eis.c if (!(e->MF[1] & MFkID) && e -> op [1] & 0000000070000) op 6822 src/dps8/dps8_eis.c op 6826 src/dps8/dps8_eis.c if (!(e->MF[2] & MFkID) && e -> op [2] & 0000000010000) op 7052 src/dps8/dps8_eis.c if (!(e->MF[0] & MFkID) && e -> op [0] & 0000000010000) op 7058 src/dps8/dps8_eis.c op 7063 src/dps8/dps8_eis.c if (!(e->MF[2] & MFkID) && e -> op [2] & 0000000777600) op 9512 src/dps8/dps8_eis.c if (!(e->MF[0] & MFkID) && e -> op [0] & 0000000077700) op 9516 src/dps8/dps8_eis.c if (!(e->MF[1] & MFkID) && e -> op [1] & 0000000007700) op 9940 src/dps8/dps8_eis.c if (!(e->MF[0] & MFkID) && e -> op [0] & 0000000007700) op 9946 src/dps8/dps8_eis.c if (!(e->MF[1] & MFkID) && e -> op [1] & 0000000077700) op 240 src/dps8/dps8_fnp2_iomcmd.c word18 op = getbits36_18 (command_data[0], 0); op 245 src/dps8/dps8_fnp2_iomcmd.c switch (op) op 385 src/dps8/dps8_fnp2_iomcmd.c sim_printf ("unknown %u. %o\n", op, op); op 1846 src/dps8/dps8_ins.c ReadInstructionFetch (cpu.PPR.IC + 1 + n, & cpu.currentEISinstruction.op[n]); op 1851 src/dps8/dps8_ins.c PNL (cpu.IWRAddr = cpu.currentEISinstruction.op[0]); op 9138 src/dps8/dps8_ins.c word36 op = M[i->address]; op 9139 src/dps8/dps8_ins.c switch (op) op 9201 src/dps8/dps8_ins.c sim_printf ("emcall unknown op %llo\n", (unsigned long long)op); op 1953 src/dps8/dps8_iom.c iom_direct_data_service_op op) op 1978 src/dps8/dps8_iom.c if (op == direct_store) op 1980 src/dps8/dps8_iom.c else if (op == direct_load) op 1982 src/dps8/dps8_iom.c else if (op == direct_read_clear) op 407 src/dps8/dps8_iom.h iom_direct_data_service_op op); op 2903 src/simh/scp.c char *ip = instr, *op, *oend, *tmpbuf; op 2925 src/simh/scp.c op = tmpbuf; op 2928 src/simh/scp.c *op++ = *ip++; op 2929 src/simh/scp.c for (; *ip && (op < oend); ) { op 2933 src/simh/scp.c *op++ = *ip++; /* copy escaped char */ op 3251 src/simh/scp.c while (*ap && (op < oend)) /* copy the argument */ op 3252 src/simh/scp.c *op++ = *ap++; op 3256 src/simh/scp.c *op++ = *ip++; op 3258 src/simh/scp.c *op = 0; /* term buffer */ op 3308 src/simh/scp.c char op[CBUFSIZE]; op 3310 src/simh/scp.c const char *op; op 3338 src/simh/scp.c (void)get_glyph (cptr, op, '"'); op 3339 src/simh/scp.c for (optr = compare_ops; optr->op; optr++) op 3340 src/simh/scp.c if (0 == strcmp (op, optr->op)) op 3342 src/simh/scp.c if (!optr->op) op 3343 src/simh/scp.c return sim_messagef (SCPE_ARG, "Invalid operator: %s\n", op); op 3344 src/simh/scp.c cptr += strlen (op); op 803 src/simh/sim_tmxr.c int32 *op; op 933 src/simh/sim_tmxr.c op = mp->lnorder; /* get line connection order list pointer */ op 938 src/simh/sim_tmxr.c if (op && (*op >= 0) && (*op < mp->lines)) /* order list present and valid? */ op 939 src/simh/sim_tmxr.c i = *op++; /* get next line in list to try */