Xn 1783 src/dps8/dps8_ins.c uint Xn = X (Td); // Get Xn of next instruction Xn 1784 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "rpt/rd/rl repeat first; X%d was %06o\n", Xn, cpu.rX[Xn]); Xn 1786 src/dps8/dps8_ins.c cpu.TPR.CA = (cpu.rX[Xn] + offset) & AMASK; Xn 1787 src/dps8/dps8_ins.c cpu.rX[Xn] = cpu.TPR.CA; Xn 1789 src/dps8/dps8_ins.c HDBGRegXW (Xn, "rpt 1st"); Xn 1791 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "rpt/rd/rl repeat first; X%d now %06o\n", Xn, cpu.rX[Xn]); Xn 2019 src/dps8/dps8_ins.c uint Xn = (uint) getbits36_3 (cpu.cu.IWB, 36 - 3); Xn 2020 src/dps8/dps8_ins.c cpu.TPR.CA = (cpu.rX[Xn] + cpu.cu.delta) & AMASK; Xn 2021 src/dps8/dps8_ins.c cpu.rX[Xn] = cpu.TPR.CA; Xn 2023 src/dps8/dps8_ins.c HDBGRegXW (Xn, "rpt delta"); Xn 2025 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD delta; X%d now %06o\n", Xn, cpu.rX[Xn]); Xn 2035 src/dps8/dps8_ins.c uint Xn = (uint) getbits36_3 (cpu.cu.IWB, 36 - 3); Xn 2036 src/dps8/dps8_ins.c cpu.TPR.CA = (cpu.rX[Xn] + cpu.cu.delta) & AMASK; Xn 2037 src/dps8/dps8_ins.c cpu.rX[Xn] = cpu.TPR.CA; Xn 2039 src/dps8/dps8_ins.c HDBGRegXW (Xn, "rpd delta even"); Xn 2041 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD delta; X%d now %06o\n", Xn, cpu.rX[Xn]); Xn 2047 src/dps8/dps8_ins.c uint Xn = (uint) getbits36_3 (cpu.cu.IRODD, 36 - 3); Xn 2048 src/dps8/dps8_ins.c cpu.TPR.CA = (cpu.rX[Xn] + cpu.cu.delta) & AMASK; Xn 2049 src/dps8/dps8_ins.c cpu.rX[Xn] = cpu.TPR.CA; Xn 2051 src/dps8/dps8_ins.c HDBGRegXW (Xn, "rpd delta odd"); Xn 2053 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD delta; X%d now %06o\n", Xn, cpu.rX[Xn]); Xn 2176 src/dps8/dps8_ins.c uint Xn = (uint) getbits36_3 (cpu.cu.IWB, 36 - 3); Xn 2179 src/dps8/dps8_ins.c cpu.rX[Xn] = cpu.lnk; Xn 2181 src/dps8/dps8_ins.c HDBGRegXW (Xn, "rl");