TA2 583 src/dps8/dps8_cpu.h # define TA2 cpu.du.TAk[1] TA2 589 src/dps8/dps8_cpu.h # define TA2 TA [1] TA2 4367 src/dps8/dps8_eis.c switch (TA2) TA2 4369 src/dps8/dps8_eis.c switch (e -> TA2) TA2 4426 src/dps8/dps8_eis.c (TA2 == 2); // (6-4 move) TA2 4429 src/dps8/dps8_eis.c (e -> TA2 == 2); // (6-4 move) TA2 4437 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR TALLY %u TA1 %u TA2 %u N1 %u N2 %u CN1 %u CN2 %u\n", cpu.du.CHTALLY, TA1, TA2, e -> N1, e -> N2, e -> CN1, e -> CN2); TA2 4439 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR TALLY %u TA1 %u TA2 %u N1 %u N2 %u CN1 %u CN2 %u\n", cpu.du.CHTALLY, e -> TA1, e -> TA2, e -> N1, e -> N2, e -> CN1, e -> CN2); TA2 4457 src/dps8/dps8_eis.c TA2 == CTA9 && TA2 4460 src/dps8/dps8_eis.c e -> TA2 == CTA9 && TA2 4497 src/dps8/dps8_eis.c TA2 == CTA9 && TA2 4500 src/dps8/dps8_eis.c e -> TA2 == CTA9 && TA2 4544 src/dps8/dps8_eis.c TA2 == CTA9 && TA2 4547 src/dps8/dps8_eis.c e -> TA2 == CTA9 && TA2 4574 src/dps8/dps8_eis.c TA2 == CTA9 && TA2 4577 src/dps8/dps8_eis.c e -> TA2 == CTA9 && TA2 4605 src/dps8/dps8_eis.c if (TA1 == TA2) TA2 4607 src/dps8/dps8_eis.c if (e -> TA1 == e -> TA2) TA2 4765 src/dps8/dps8_eis.c switch (TA2) TA2 4767 src/dps8/dps8_eis.c switch (e -> TA2) TA2 4821 src/dps8/dps8_eis.c (TA2 == 2); // (6-4 move) TA2 4824 src/dps8/dps8_eis.c (e -> TA2 == 2); // (6-4 move) TA2 4839 src/dps8/dps8_eis.c TA2 == CTA9 && TA2 4842 src/dps8/dps8_eis.c e -> TA2 == CTA9 && TA2 4870 src/dps8/dps8_eis.c TA2 == CTA9 && TA2 4873 src/dps8/dps8_eis.c e -> TA2 == CTA9 && TA2 4905 src/dps8/dps8_eis.c if (TA1 == TA2) TA2 4907 src/dps8/dps8_eis.c if (e -> TA1 == e -> TA2) TA2 7079 src/dps8/dps8_eis.c uint dstTA = TA2; TA2 7084 src/dps8/dps8_eis.c uint dstTA = e->TA2; TA2 7101 src/dps8/dps8_eis.c switch (TA2) TA2 7103 src/dps8/dps8_eis.c switch (e -> TA2) TA2 7194 src/dps8/dps8_eis.c if (TA1 == TA2) TA2 7196 src/dps8/dps8_eis.c if (e->TA1 == e->TA2)