reg               327 src/dps8/dps8_eis.c static word36 getCrAR (word4 reg)
reg               329 src/dps8/dps8_eis.c     if (reg == 0)
reg               332 src/dps8/dps8_eis.c     if (reg & 010) /* Xn */
reg               333 src/dps8/dps8_eis.c       return cpu.rX [X (reg)];
reg               335 src/dps8/dps8_eis.c     switch (reg)
reg              1294 src/dps8/dps8_eis.c         uint reg = opDesc & 017;
reg              1296 src/dps8/dps8_eis.c         address += getMFReg18 (reg, false, true, mod_fault); // ID=1: disallow du, allow n,ic
reg              1440 src/dps8/dps8_eis.c         uint reg = opDesc & 017;
reg              1442 src/dps8/dps8_eis.c         e -> N [k - 1] = (uint) getMFReg36 (reg, false, false, mod_fault); // RL=1: disallow du,n,ic
reg              1714 src/dps8/dps8_eis.c         uint reg = opDesc & 017;
reg              1715 src/dps8/dps8_eis.c         e->N[k-1] = getMFReg18(reg, false, false, mod_fault) & 077; // RL=1: disallow du,n,ic
reg              1876 src/dps8/dps8_eis.c         uint reg = opDesc & 017;
reg              1877 src/dps8/dps8_eis.c         e->N[k-1] = getMFReg36(reg, false, false, mod_fault) & 077777777;  // RL=1: disallow du,n,ic
reg              1878 src/dps8/dps8_eis.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "bitstring k %d RL reg %u val %"PRIo64"\n", k, reg, (word36)e->N[k-1]);
reg              1966 src/dps8/dps8_eis.c     word4 reg = GET_TD (cpu.cu.IWB); // 4-bit register modification (None except
reg              1969 src/dps8/dps8_eis.c     word36 ur = getCrAR (reg);
reg              2045 src/dps8/dps8_eis.c     word4 reg = GET_TD (cpu.cu.IWB); // 4-bit register modification (None except
reg              2048 src/dps8/dps8_eis.c     word36 ur = getCrAR (reg);
reg              2092 src/dps8/dps8_eis.c     word6 reg = GET_TD (cpu.cu.IWB); // 4-bit register modification (None except
reg              2095 src/dps8/dps8_eis.c     word36 rcnt = getCrAR (reg);
reg              2109 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "axbd sz %d ARn 0%o address 0%o reg 0%o r 0%o\n", sz, ARn, address, reg, r);
reg              2164 src/dps8/dps8_eis.c     word4 reg = (word4) GET_TD (cpu.cu.IWB);
reg              2166 src/dps8/dps8_eis.c     word24 r = getCrAR ((word4) reg) & MASK24;
reg              2226 src/dps8/dps8_eis.c 
reg              2229 src/dps8/dps8_eis.c 
reg              2365 src/dps8/dps8_eis.c     word4 reg = (word4) GET_TD (cpu.cu.IWB);
reg              2368 src/dps8/dps8_eis.c     int32_t r = (int32_t) (getCrAR (reg) & MASK18);
reg              2372 src/dps8/dps8_eis.c                "awd ARn 0%o address 0%o reg 0%o r 0%o\n", ARn, address, reg, r);
reg              2402 src/dps8/dps8_eis.c     word4 reg = (word4) GET_TD (cpu.cu.IWB);
reg              2404 src/dps8/dps8_eis.c     word24 r = getCrAR ((word4) reg) & MASK24;
reg              2440 src/dps8/dps8_eis.c     word4 reg = (word4) GET_TD (cpu.cu.IWB);
reg              2443 src/dps8/dps8_eis.c     int32_t r = (int32_t) (getCrAR (reg) & MASK18);
reg              2446 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "swd ARn 0%o address 0%o reg 0%o r 0%o\n", ARn, address, reg, r);
reg              2478 src/dps8/dps8_eis.c     word4 reg = (word4) GET_TD (cpu.cu.IWB);
reg              2481 src/dps8/dps8_eis.c     word21 r = getCrAR (reg) & MASK21;;
reg              2485 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "s9bd ARn 0%o address 0%o reg 0%o r 0%o\n", ARn, address, reg, r);
reg              2759 src/dps8/dps8_eis.c     word4 reg = (word4) GET_TD (cpu.cu.IWB); // 4-bit register modification (None except
reg              2767 src/dps8/dps8_eis.c     word36 rcnt = getCrAR (reg);
reg              2785 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "asxbd sz %d ARn 0%o address 0%o reg 0%o r 0%o\n", sz, ARn, address, reg, r);
reg              7328 src/dps8/dps8_ins.c                     uint reg = cpu.tweaks.l68_mode ? L68_APU_HIST_REG : DPS8M_APU_HIST_REG;
reg              7329 src/dps8/dps8_ins.c                     cpu.Ypair[0] = cpu.history[reg] [cpu.history_cyclic[reg]][0];
reg              7330 src/dps8/dps8_ins.c                     cpu.Ypair[1] = cpu.history[reg] [cpu.history_cyclic[reg]][1];
reg              7331 src/dps8/dps8_ins.c                     cpu.history_cyclic[reg] = (cpu.history_cyclic[reg] + 1) % N_MODEL_HIST_SIZE;
reg              7376 src/dps8/dps8_ins.c                     uint reg = cpu.tweaks.l68_mode ? L68_DU_HIST_REG : DPS8M_EAPU_HIST_REG;
reg              7377 src/dps8/dps8_ins.c                     cpu.Ypair[0] = cpu.history[reg] [cpu.history_cyclic[reg]][0];
reg              7378 src/dps8/dps8_ins.c                     cpu.Ypair[1] = cpu.history[reg] [cpu.history_cyclic[reg]][1];
reg              7379 src/dps8/dps8_ins.c                     cpu.history_cyclic[reg] = (cpu.history_cyclic[reg] + 1) % N_MODEL_HIST_SIZE;
reg              7398 src/dps8/dps8_ins.c                     uint reg = cpu.tweaks.l68_mode ? L68_OU_HIST_REG : DPS8M_DU_OU_HIST_REG;
reg              7399 src/dps8/dps8_ins.c                     cpu.Ypair[0] = cpu.history[reg] [cpu.history_cyclic[reg]][0];
reg              7400 src/dps8/dps8_ins.c                     cpu.Ypair[1] = cpu.history[reg] [cpu.history_cyclic[reg]][1];
reg              7401 src/dps8/dps8_ins.c                     cpu.history_cyclic[reg] = (cpu.history_cyclic[reg] + 1) % N_MODEL_HIST_SIZE;
reg                94 src/dps8/hdbg.c     } reg;
reg               257 src/dps8/hdbg.c   hevents[p].reg.type = type;
reg               258 src/dps8/hdbg.c   hevents[p].reg.data = data;
reg               264 src/dps8/hdbg.c   hevents[p].reg.type = type;
reg               265 src/dps8/hdbg.c   hevents[p].reg.data = data;
reg               408 src/dps8/hdbg.c   if (p->reg.type == hreg_IR)
reg               414 src/dps8/hdbg.c              regNames[p->reg.type],
reg               415 src/dps8/hdbg.c              (unsigned long long int)p->reg.data,
reg               416 src/dps8/hdbg.c              TSTF (p->reg.data, I_ZERO),
reg               417 src/dps8/hdbg.c              TSTF (p->reg.data, I_NEG),
reg               418 src/dps8/hdbg.c              TSTF (p->reg.data, I_CARRY),
reg               419 src/dps8/hdbg.c              TSTF (p->reg.data, I_OFLOW),
reg               420 src/dps8/hdbg.c              TSTF (p->reg.data, I_TALLY));
reg               421 src/dps8/hdbg.c   else if (p->reg.type >= hreg_X0 && p->reg.type <= hreg_X7)
reg               427 src/dps8/hdbg.c              regNames[p->reg.type],
reg               428 src/dps8/hdbg.c              (unsigned long long int)p->reg.data);
reg               435 src/dps8/hdbg.c              regNames[p->reg.type],
reg               436 src/dps8/hdbg.c              (unsigned long long int)p->reg.data);
reg               441 src/dps8/hdbg.c   if (p->reg.type >= hreg_PR0 && p->reg.type <= hreg_PR7)
reg               447 src/dps8/hdbg.c              regNames[p->reg.type],
reg               457 src/dps8/hdbg.c              regNames[p->reg.type],
reg               471 src/dps8/hdbg.c            regNames[p->reg.type],