rd                485 src/dps8/dps8_addrmods.c         if (cpu.cu.rpt || cpu.cu.rd | cpu.cu.rl)
rd                532 src/dps8/dps8_addrmods.c             if (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl)
rd                587 src/dps8/dps8_addrmods.c             if (!(cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl))
rd                622 src/dps8/dps8_addrmods.c         if (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl)
rd               2436 src/dps8/dps8_cpu.c                        cpu.cu.rpt | cpu.cu.rd | cpu.cu.rl))
rd               2905 src/dps8/dps8_cpu.c                    (cpu.cu.rd && (cpu.PPR.IC & 1)) ||
rd               2909 src/dps8/dps8_cpu.c                   if (cpu.cu.rd)
rd               3005 src/dps8/dps8_cpu.c                   !cpu.cu.repeat_first && !cpu.cu.rpt && !cpu.cu.rd && !cpu.cu.rl &&
rd               1012 src/dps8/dps8_cpu.h     word1 rd;      // 20    RD  Execute an Repeat Double (rpd) instruction
rd               1037 src/dps8/dps8_cpu.h #define USE_IRODD (cpu.cu.rd && ((cpu. PPR.IC & 1) != 0))
rd                443 src/dps8/dps8_ins.c     putbits36 (& words[5], 20,  1, cpu.cu.rd);
rd                560 src/dps8/dps8_ins.c     cpu.cu.rd           = false;
rd                664 src/dps8/dps8_ins.c     cpu.cu.rd           = getbits36_1  (words[5], 20);
rd               1098 src/dps8/dps8_ins.c     if (cpu.cu.rd && ((cpu.PPR.IC & 1) != 0))
rd               1106 src/dps8/dps8_ins.c     else if (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl)
rd               1274 src/dps8/dps8_ins.c     if (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl)
rd               1290 src/dps8/dps8_ins.c     if (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl)
rd               1482 src/dps8/dps8_ins.c   if (unlikely (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl)) {
rd               1515 src/dps8/dps8_ins.c     if (unlikely (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl)) {
rd               1694 src/dps8/dps8_ins.c   if (unlikely (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl)) {
rd               1753 src/dps8/dps8_ins.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD first %d rpt %d rd %d e/o %d X0 %06o a %d b %d\n", cpu.cu.repeat_first, cpu.cu.rpt, cpu.cu.rd, cpu.PPR.IC & 1, cpu.rX[0], !! (cpu.rX[0] & 01000), !! (cpu.rX[0] & 0400));
rd               1767 src/dps8/dps8_ins.c       if (cpu.cu.rpt || (cpu.cu.rd && icOdd) || cpu.cu.rl)
rd               1774 src/dps8/dps8_ins.c          (cpu.cu.rd && icEven) ||   // rpd & even
rd               1775 src/dps8/dps8_ins.c          (cpu.cu.rd && icOdd)  ||   // rpd & odd
rd               2000 src/dps8/dps8_ins.c   if (rf && cpu.cu.rd && icEven)
rd               2003 src/dps8/dps8_ins.c   if (unlikely ((! rf) && (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl))) {
rd               2009 src/dps8/dps8_ins.c     if (cpu.cu.rpt || cpu.cu.rd) {
rd               2015 src/dps8/dps8_ins.c       sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD delta first %d rf %d rpt %d rd %d " "e/o %d X0 %06o a %d b %d\n", cpu.cu.repeat_first, rf, cpu.cu.rpt, cpu.cu.rd, icOdd, cpu.rX[0], rptA, rptB);
rd               2032 src/dps8/dps8_ins.c       if (cpu.cu.rd && icOdd && rptA) { // rpd, even instruction
rd               2044 src/dps8/dps8_ins.c       if (cpu.cu.rd && icOdd && rptB) { // rpdb, odd instruction
rd               2072 src/dps8/dps8_ins.c       flt = (cpu.cu.rl || cpu.cu.rpt || cpu.cu.rd) && cpu.dlyFlt; // L68
rd               2084 src/dps8/dps8_ins.c     if (cpu.cu.rpt || (cpu.cu.rd && icOdd) || cpu.cu.rl) {
rd               2159 src/dps8/dps8_ins.c         cpu.cu.rd = false;
rd               2171 src/dps8/dps8_ins.c         cpu.cu.rd = false;
rd               2238 src/dps8/dps8_ins.c             if (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl)
rd               6923 src/dps8/dps8_ins.c             cpu.cu.rd = 1;
rd               1047 src/simh/sim_sock.c int sim_check_conn (SOCKET sock, int rd)
rd               1065 src/simh/sim_sock.c if (rd)
rd                100 src/simh/sim_sock.h int sim_check_conn (SOCKET sock, int rd);