op 3983 src/decNumber/decNumber.c decContext *set, Flag op, uInt *status) { op 4054 src/decNumber/decNumber.c op & (REMAINDER | REMNEAR)) { // as is remainder of infinity op 4065 src/decNumber/decNumber.c if (op&(REMAINDER|REMNEAR)) { op 4074 src/decNumber/decNumber.c if (op&DIVIDE) { op 4092 src/decNumber/decNumber.c if (op&(REMAINDER|REMNEAR)) *status|=DEC_Invalid_operation; op 4106 src/decNumber/decNumber.c if (op&DIVIDE) { op 4112 src/decNumber/decNumber.c else if (op&DIVIDEINT) { op 4137 src/decNumber/decNumber.c if (exponent<0 && !(op==DIVIDE)) { op 4138 src/decNumber/decNumber.c if (op&DIVIDEINT) { op 4148 src/decNumber/decNumber.c if (op&REMAINDER || exponent<-1) { op 4189 src/decNumber/decNumber.c if (!(op&DIVIDE)) var1units++; op 4240 src/decNumber/decNumber.c if (!(op&DIVIDE)) { op 4343 src/decNumber/decNumber.c if (op&(REMAINDER|REMNEAR)) break; op 4344 src/decNumber/decNumber.c if ((op&DIVIDE) && (exponent<=maxexponent)) break; op 4349 src/decNumber/decNumber.c if (exponent==0 && !(op&DIVIDE)) break; op 4371 src/decNumber/decNumber.c if (op&DIVIDE) { op 4411 src/decNumber/decNumber.c if (op & (REMAINDER|REMNEAR)) { op 4460 src/decNumber/decNumber.c if (op&REMNEAR) { op 4544 src/decNumber/decNumber.c if (!set->extended && (op==DIVIDE)) decTrim(res, set, 0, 1, &dropped); op 5729 src/decNumber/decNumber.c Flag op, uInt *status) { op 5756 src/decNumber/decNumber.c if (op==COMPTOTAL) { // total ordering op 5775 src/decNumber/decNumber.c if (op==COMPARE); // result will be NaN op 5776 src/decNumber/decNumber.c else if (op==COMPSIG) // treat qNaN as sNaN op 5778 src/decNumber/decNumber.c else if (op==COMPTOTAL) { // total ordering, always finite op 5801 src/decNumber/decNumber.c op=COMPMAX; op 5807 src/decNumber/decNumber.c op=COMPNAN; // use special path op 5812 src/decNumber/decNumber.c if (op==COMPMAXMAG || op==COMPMINMAG) result=decCompare(lhs, rhs, 1); op 5818 src/decNumber/decNumber.c if (op==COMPARE || op==COMPSIG ||op==COMPTOTAL) { // returning signum op 5819 src/decNumber/decNumber.c if (op==COMPTOTAL && result==0) { op 5834 src/decNumber/decNumber.c else if (op==COMPNAN); // special, drop through op 5845 src/decNumber/decNumber.c op=COMPMAX; op 5867 src/decNumber/decNumber.c if (op==COMPMIN || op==COMPMINMAG) result=-result; op 4288 src/dps8/dps8_cpu.c void add_l68_APU_history (enum APUH_e op) op 4293 src/dps8/dps8_cpu.c w0 = op; // set 17-24 FDSPTW/.../FAP bits op 539 src/dps8/dps8_cpu.h word36 op [3]; // raw operand descriptors op 540 src/dps8/dps8_cpu.h #define OP1 op [0] // 1st descriptor (2nd ins word) op 541 src/dps8/dps8_cpu.h #define OP2 op [1] // 2nd descriptor (3rd ins word) op 542 src/dps8/dps8_cpu.h #define OP3 op [2] // 3rd descriptor (4th ins word) op 2379 src/dps8/dps8_cpu.h void add_l68_APU_history (enum APUH_e op); op 1189 src/dps8/dps8_eis.c word36 opDesc = e -> op [k - 1]; op 1308 src/dps8/dps8_eis.c e -> op [k - 1] = EISRead (& e -> addr [k - 1]); op 1348 src/dps8/dps8_eis.c word36 opDesc = e -> op [k - 1]; op 1602 src/dps8/dps8_eis.c word36 opDesc = e -> op [k - 1]; op 1661 src/dps8/dps8_eis.c word36 opDesc = e->op[k-1]; op 1836 src/dps8/dps8_eis.c word36 opDesc = e->op[k-1]; op 3004 src/dps8/dps8_eis.c if (!(e->MF[0] & MFkID) && e -> op [0] & 0000000010000) op 3015 src/dps8/dps8_eis.c op 3145 src/dps8/dps8_eis.c if (!(e->MF[0] & MFkID) && e -> op [0] & 0000000010000) op 3149 src/dps8/dps8_eis.c if (!(e->MF[2] & MFkID) && e -> op [2] & 0000000777660) op 3328 src/dps8/dps8_eis.c if (!(e->MF[0] & MFkID) && e -> op [0] & 0000000010000) op 3332 src/dps8/dps8_eis.c if (!(e->MF[2] & MFkID) && e -> op [2] & 0000000777660) op 3527 src/dps8/dps8_eis.c if (!(e->MF[0] & MFkID) && e -> op [0] & 0000000010000) op 3531 src/dps8/dps8_eis.c if (!(e->MF[2] & MFkID) && e -> op [2] & 0000000777660) op 3695 src/dps8/dps8_eis.c if (!(e->MF[0] & MFkID) && e -> op [0] & 0000000010000) op 3703 src/dps8/dps8_eis.c if (!(e->MF[2] & MFkID) && e -> op [2] & 0000000777660) op 3896 src/dps8/dps8_eis.c if (!(e->MF[0] & MFkID) && e -> op [0] & 0000000010000) op 3900 src/dps8/dps8_eis.c if (!(e->MF[1] & MFkID) && e -> op [1] & 0000000777660) op 3904 src/dps8/dps8_eis.c if (!(e->MF[2] & MFkID) && e -> op [2] & 0000000777660) op 4091 src/dps8/dps8_eis.c if (!(e->MF[0] & MFkID) && e -> op [0] & 0000000010000) op 4095 src/dps8/dps8_eis.c if (!(e->MF[1] & MFkID) && e -> op [1] & 0000000777660) op 4099 src/dps8/dps8_eis.c if (!(e->MF[2] & MFkID) && e -> op [2] & 0000000777660) op 4330 src/dps8/dps8_eis.c if (!(e->MF[0] & MFkID) && e -> op [0] & 0000000010000) op 4334 src/dps8/dps8_eis.c if (!(e->MF[1] & MFkID) && e -> op [1] & 0000000010000) op 4728 src/dps8/dps8_eis.c if (!(e->MF[0] & MFkID) && e -> op [0] & 0000000010000) op 4732 src/dps8/dps8_eis.c if (!(e->MF[1] & MFkID) && e -> op [1] & 0000000010000) op 6684 src/dps8/dps8_eis.c if (!(e->MF[0] & MFkID) && e -> op [0] & 0000000010000) op 6689 src/dps8/dps8_eis.c op 6693 src/dps8/dps8_eis.c if (!(e->MF[1] & MFkID) && e -> op [1] & 0000000010000) op 6697 src/dps8/dps8_eis.c if (!(e->MF[2] & MFkID) && e -> op [2] & 0000000010000) op 6814 src/dps8/dps8_eis.c op 6818 src/dps8/dps8_eis.c if (!(e->MF[1] & MFkID) && e -> op [1] & 0000000070000) op 6823 src/dps8/dps8_eis.c op 6827 src/dps8/dps8_eis.c if (!(e->MF[2] & MFkID) && e -> op [2] & 0000000010000) op 7053 src/dps8/dps8_eis.c if (!(e->MF[0] & MFkID) && e -> op [0] & 0000000010000) op 7059 src/dps8/dps8_eis.c op 7064 src/dps8/dps8_eis.c if (!(e->MF[2] & MFkID) && e -> op [2] & 0000000777600) op 9513 src/dps8/dps8_eis.c if (!(e->MF[0] & MFkID) && e -> op [0] & 0000000077700) op 9517 src/dps8/dps8_eis.c if (!(e->MF[1] & MFkID) && e -> op [1] & 0000000007700) op 9941 src/dps8/dps8_eis.c if (!(e->MF[0] & MFkID) && e -> op [0] & 0000000007700) op 9947 src/dps8/dps8_eis.c if (!(e->MF[1] & MFkID) && e -> op [1] & 0000000077700) op 240 src/dps8/dps8_fnp2_iomcmd.c word18 op = getbits36_18 (command_data[0], 0); op 245 src/dps8/dps8_fnp2_iomcmd.c switch (op) op 385 src/dps8/dps8_fnp2_iomcmd.c sim_printf ("unknown %u. %o\n", op, op); op 1828 src/dps8/dps8_ins.c Read (cpu.PPR.IC + 1 + n, & cpu.currentEISinstruction.op[n], INSTRUCTION_FETCH); op 1831 src/dps8/dps8_ins.c PNL (cpu.IWRAddr = cpu.currentEISinstruction.op[0]); op 9116 src/dps8/dps8_ins.c word36 op = M[i->address]; op 9117 src/dps8/dps8_ins.c switch (op) op 9179 src/dps8/dps8_ins.c sim_printf ("emcall unknown op %llo\n", (unsigned long long)op); op 1953 src/dps8/dps8_iom.c iom_direct_data_service_op op) op 1978 src/dps8/dps8_iom.c if (op == direct_store) op 1980 src/dps8/dps8_iom.c else if (op == direct_load) op 1982 src/dps8/dps8_iom.c else if (op == direct_read_clear) op 407 src/dps8/dps8_iom.h iom_direct_data_service_op op); op 2902 src/simh/scp.c char *ip = instr, *op, *oend, *tmpbuf; op 2924 src/simh/scp.c op = tmpbuf; op 2927 src/simh/scp.c *op++ = *ip++; op 2928 src/simh/scp.c for (; *ip && (op < oend); ) { op 2932 src/simh/scp.c *op++ = *ip++; /* copy escaped char */ op 3250 src/simh/scp.c while (*ap && (op < oend)) /* copy the argument */ op 3251 src/simh/scp.c *op++ = *ap++; op 3255 src/simh/scp.c *op++ = *ip++; op 3257 src/simh/scp.c *op = 0; /* term buffer */ op 3307 src/simh/scp.c char op[CBUFSIZE]; op 3309 src/simh/scp.c const char *op; op 3337 src/simh/scp.c (void)get_glyph (cptr, op, '"'); op 3338 src/simh/scp.c for (optr = compare_ops; optr->op; optr++) op 3339 src/simh/scp.c if (0 == strcmp (op, optr->op)) op 3341 src/simh/scp.c if (!optr->op) op 3342 src/simh/scp.c return sim_messagef (SCPE_ARG, "Invalid operator: %s\n", op); op 3343 src/simh/scp.c cptr += strlen (op); op 767 src/simh/sim_tmxr.c int32 *op; op 839 src/simh/sim_tmxr.c op = mp->lnorder; /* get line connection order list pointer */ op 844 src/simh/sim_tmxr.c if (op && (*op >= 0) && (*op < mp->lines)) /* order list present and valid? */ op 845 src/simh/sim_tmxr.c i = *op++; /* get next line in list to try */