enable 147 src/dps8/dps8_cpu.c 'A' + i, cpus[cpu_unit_idx].switches.enable [i]); enable 495 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [port_num] = (uint) v; enable 591 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [0] = false; enable 597 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [1] = true; enable 603 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [2] = false; enable 609 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [3] = false; enable 616 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [4] = false; enable 622 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [5] = false; enable 628 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [6] = false; enable 634 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [7] = false; enable 640 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [1] = true; enable 793 src/dps8/dps8_cpu.c cpun->switches.enable[port_num] = 1; enable 800 src/dps8/dps8_cpu.c cpun->switches.enable[port_num] = 0; enable 818 src/dps8/dps8_cpu.c cpun->switches.enable[port_num] = 1; enable 825 src/dps8/dps8_cpu.c cpun->switches.enable[port_num] = 0; enable 1261 src/dps8/dps8_cpu.c if (! cpu.switches.enable [port_num]) enable 715 src/dps8/dps8_cpu.h uint enable [N_CPU_PORTS]; enable 7845 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [0] & 01LL) enable 7856 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [1] & 01LL) enable 7867 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [2] & 01LL) enable 7878 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [3] & 01LL) enable 8068 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [4] & 01LL) enable 8079 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [5] & 01LL) enable 8090 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [6] & 01LL) enable 8101 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [7] & 01LL)