This post is going to discuss some of the specifics of the FPGA implementation of the Honeywell DATANET 6678 Front-End Network Processor.

First off, one of the main goals of this project, aside from achieving the end result, is to gain a thorough understanding of FPGA design and programming. To help accomplish this goal, I am reading the book “Computer Architecture Tutorial Using an FPGA” by Robert Dunne. This book provides excellent tutorials on FPGA programming using Verilog with the Terasic DE-10 Lite development board and offers a detailed guide on implementing a 32-bit ARM processor. I highly recommend this book.

We’re excited to announce an ambitious long-term project, currently in the early stages, to implement as much of the DPS‑8/M mainframe architecture as possible using one (or more) FPGAs — with the ability to run the full Multics operating system — is now underway, led by Dean S. Anderson.

In the early 1980s, Dean started as a computer operator at Gelco on a large Honeywell Series‑60 ∕ Level‑66 dual processor mainframe (eventually converted to a four processor DPS‑8) running GCOS‑3. Over time, he worked his way through Gelco’s Production Control and Special Projects groups writing programs to automate the Computer Operations Department. This included writing GCOS‑3 kernel modifications for special handling of tapes.